Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

3.7.6.1.1. Requested Handler Address

The RHA specifies the address of the handler associated with the interrupt. The availability of an RHA for each interrupt allows the Nios® II processor to jump directly to the interrupt handler, reducing interrupt latency.

The RHA for each interrupt is typically software-configurable. The method for specifying the RHA is dependent on the specific EIC implementation.

If the Nios® II processor is implemented with an MMU, the processor treats handler addresses as virtual addresses.

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