Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

3.7.7.6. Supervisor-Only Instruction Address

When your system contains an MMU and the processor is in user mode (status.U = 1), attempts to access a supervisor-only instruction address result in a supervisor-only instruction address exception. Any instruction fetch can cause this exception. For definitions of supervisor-only address ranges, refer to the Virtual Memory Partitions Table.

This exception is implemented only in Nios® II processors that include the MMU.

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