Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

2.5.3. Internal Interrupt Controller

The Nios II architecture supports 32 internal hardware interrupts. The processor core has 32 level-sensitive interrupt request (IRQ) inputs, irq0 through irq31, providing a unique input for each interrupt source. IRQ priority is determined by software. The architecture supports nested interrupts.

Your software can enable and disable any interrupt source individually through the ienable control register, which contains an interrupt-enable bit for each of the IRQ inputs. Software can enable and disable interrupts globally using the PIE bit of the status control register. A hardware interrupt is generated if and only if all of the following conditions are true:

  • The PIE bit of the status register is 1
  • An interrupt-request input, irq<n>, is asserted
  • The corresponding bit n of the ienable register is 1

The interrupt vector custom instruction is less efficient than using the EIC interface with the Intel FPGA vectored interrupt controller component, and thus is deprecated in Platform Designer. Intel recommends using the EIC interface.

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