Nios® II Processor Reference Guide

ID 683836
Date 8/28/2023
Public
Document Table of Contents

5.2.10. ECC

The Nios® II/f core has the option to add ECC support for the following Nios® II internal RAM blocks.
  • Instruction cache
    • ECC errors (1, 2, or 3 bits) that occur in the instruction cache are recoverable; the Nios® II processor flushes the cache line and reads from external memory instead of correcting the ECC error.
  • Register file
    • 1 bit ECC errors are recoverable
    • 2 bit ECC errors are not recoverable and generate ECC exceptions
  • MMU TLB
    • 1 bit ECC errors triggered by hardware reads are recoverable
    • 2 bit ECC errors triggered by hardware reads are not recoverable and generate ECC exception.
    • 1 or 2 bit ECC errors triggered by software reads to the TLBMISC register do not trigger an exception, instead, TLBMISC.EE is set to 1. Software must read this field and invalidate/overwrite the TLB entry.
  • Data Cache
    • tag RAM—The ECCINJ.DCTAG field is used to inject ECC errors into the tag RAM.
    • data RAM—The ECCINJ.DCDAT field is used to inject ECC errors into the data RAM
  • Tightly-Coupled Memories (TCMs)— Nios® II includes the ECC encoder/decoder logic for each TCM and the TCM master port data width is increased to allow the Nios® II to read and write the ECC parity bits.The TCM must be a RAM and must store the ECC parity bits along with the data bits.
    • Instruction Tightly-Coupled Memories (ITCM)— Nios® II supports up to 4 ITCMs
    • Data Tightly-Coupled Memories (DTCM)— Nios® II supports up to 4 DTCMs

The ECC interface is an Avalon® -ST source with the output signal ecc_event_bus. This interface allows external logic to monitor ECC errors in the Nios® II processor.

Table 67.  ECC Error Signals
Bit Field Description Effect on Software Available
0 EEH ECC error exception while in exception handler mode (i.e., STATUS.EH = 1). Likely fatal Always
1 RF_RE Recoverable (1 bit) ECC error in register file RAM None Always
2 RF_UE Unrecoverable (2 bit) ECC error in register file RAM Likely fatal Always
3 ICTAG_RE Recoverable (1, 2, or 3 bit) ECC error in instruction cache tag RAM None Instruction cache present
4 ICDAT_RE Recoverable (1, 2, or 3 bit) ECC error in instruction cache data RAM. None Instruction cache present
5 ITCM0_RE Recoverable (1-bit) ECC error in ITCM0 None ITCM0 present
6 ITCM0_UE Unrecoverable (2-bit) ECC error in ITCM0 Possibly fatal ITCM0 present
7 ITCM1_RE Recoverable (1-bit) ECC error in ITCM1 None ITCM1 present
8 ITCM1_UE Unrecoverable (2-bit) ECC error in ITCM1 Likely fatal ITCM1 present
9 ITCM2_RE Recoverable (1-bit) ECC error in ITCM2 None ITCM2 present
10 ITCM2_UE Unrecoverable (2-bit) ECC error in ITCM2 Likely fatal ITCM2 present
11 ITCM3_RE Recoverable (1-bit) ECC error in ITCM3 None ITCM3 present
12 ITCM3_UE Unrecoverable (2-bit) ECC error in ITCM3 Likely fatal ITCM3 present
13 DCTAG_RE Recoverable (1-bit) ECC error in data cache tag RAM None Data cache present
14 DCTAG_UE Unrecoverable (2-bit) ECC error in data cache tag RAM Likely fatal Data cache present
15 DCDAT_RE Recoverable (1-bit with dirty line, 2-bit or 3-bit with clean line) ECC error in data cache data RAM. Excludes recoverable errors found during writeback of a dirty line. None Data cache present
16 DCDAT_UE Unrecoverable (2-bit with dirty line) ECC error in data cache data RAM. Excludes unrecoverable errors found during writeback of a dirty line. Likely fatal Data cache present
17 DCWB_RE Recoverable (1-bit) ECC error in data cache data RAM or victim line buffer RAM during writeback of a dirty line. None Data cache present
18 DCWB_UE Unrecoverable (2-bit) ECC error in data cache data RAM or victim line buffer RAM during writeback of a dirty line. Likely fatal Data cache present
19 TLB_RE Recoverable (1 bit) ECC error in TLB RAM (hardware read of TLB) None MMU present
20 TLB_UE Unrecoverable (2 bit) ECC error in TLB RAM (hardware read of TLB) Possibly fatal MMU present
21 TLB_SW Software-triggered (1, 2, or 3 bit) ECC error in software read of TLB Possibly fatal MMU present
22 DTCM0_RE Recoverable (1-bit) ECC error in DTCM0 None DTCM0 present
23 DTCM0_UE Unrecoverable (2-bit) ECC error in DTCM0 Likely fatal DTCM0 present
24 DTCM1_RE Recoverable (1-bit) ECC error in DTCM1 None DTCM1 present
25 DTCM1_UE Unrecoverable (2-bit) ECC error in DTCM1 Likely fatal DTCM1 present
26 DTCM2_RE Recoverable (1-bit) ECC error in DTCM2 None DTCM2 present
27 DTCM2_UE Unrecoverable (2-bit) ECC error in DTCM2 Likely fatal DTCM2 present
28 DTCM3_RE Recoverable (1-bit) ECC error in DTCM3 None DTCM3 present
29 DTCM3_UE Unrecoverable (2-bit) ECC error in DTCM3 Likely fatal DTCM3 present