Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Document Table of Contents

3.6.1. Enabling ECC

The ECC is disabled on system reset. Before enabling the ECC, initialize the Nios® II RAM blocks to avoid spurious ECC errors.

The Nios® II processor executes the INITI instruction on each cache line, which initializes the instruction cache RAM. The RAM does not require special initialization because any detected ECC errors are ignored if the line is invalid; the line is invalid after INITI instructions initialize the tag RAM.

Nios® II processor instructions that write to every register (except register 0) initialize the register file RAM blocks. If shadow register sets are present, this step is performed for all registers in the shadow register set using the WRPRS instruction.

Nios® II processor instructions that write every TLB RAM location initialize the MMU TLB RAM. This RAM does not require special initialization.

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