Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

5.2.3.2.1. Instruction Cache

The instruction cache memory has the following characteristics:
  • Direct-mapped cache implementation.
  • 32 bytes (8 words) per cache line.
  • The instruction master port reads an entire cache line at a time from memory, and issues one read per clock cycle.
  • Critical word first.
  • Virtually-indexed, physically-tagged, when MMU present.

The size of the tag field depends on the size of the cache memory and the physical address size. The size of the line field depends only on the size of the cache memory. The offset field is always five bits (i.e., a 32-byte line). The maximum instruction byte address size is 31 bits in systems without an MMU present. In systems with an MMU, the maximum instruction byte address size is 32 bits and the tag field always includes all the bits of the physical frame number (PFN).

The instruction cache is optional. However, excluding instruction cache from the Nios II/f core requires that the core include at least one tightly-coupled instruction memory.

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