Nios® II Processor Reference Guide

ID 683836
Date 8/28/2023
Document Table of Contents

1.1. Nios® II Processor System Basics

The Nios® II processor is a general-purpose RISC processor core with the following features:
  • Full 32-bit instruction set, data path, and address space
  • 32 general-purpose registers
  • Optional shadow register sets
  • 32 interrupt sources
  • External interrupt controller interface for more interrupt sources
  • Single-instruction 32 × 32 multiply and divide producing a 32-bit result
  • Dedicated instructions for computing 64-bit and 128-bit products of multiplication
  • Optional floating-point instructions for single-precision floating-point operations
  • Single-instruction barrel shifter
  • Access to a variety of on-chip peripherals, and interfaces to off-chip memories and peripherals
  • Hardware-assisted debug module enabling processor start, stop, step, and trace under control of the Nios II software development tools
  • Optional memory management unit (MMU) to support operating systems that require MMUs
  • Optional memory protection unit (MPU)
  • Software development environment based on the GNU C/C++ tool chain and the Nios II Software Build Tools (SBT) for Eclipse
  • Integration with Intel FPGA’s Signal Tap II* Embedded Logic Analyzer, enabling real-time analysis of instructions and data along with other signals in the FPGA design
  • Instruction set architecture (ISA) compatible across all Nios® II processor systems
  • Performance up to 250 DMIPS
  • Error correcting code (ECC) support for all Nios® II processor internal RAM blocks

A Nios® II processor system is equivalent to a microcontroller or “computer on a chip” that includes a processor and a combination of peripherals and memory on a single chip. A Nios® II processor system consists of a Nios® II processor core, a set of on-chip peripherals, on-chip memory, and interfaces to off-chip memory, all implemented on a single Intel FPGA device. Like a microcontroller family, all Nios® II processor systems use a consistent instruction set and programming model.