18.104.22.168. The badaddr Register
Nios® II/f processor provides information useful to system software for exception processing in the exception and badaddr registers when an exception occurs.
When an exception occurs in Nios® II/f processor, the badaddr register contains the byte instruction or data address associated with certain exceptions at the time the exception occurred. The Nios® II Exceptions Table lists which exceptions write the badaddr register along with the value written.
|BADDR||BADDR contains the byte instruction address or data address associated with an exception when certain exceptions occur. The Address column of the Nios® II Exceptions Table lists which exceptions write the BADDR field.||Read||0||Only with Nios® II/f|
The BADDR field allows up to a 32-bit instruction address or data address. If an MMU or MPU is present, the BADDR field is 32 bits because MMU and MPU instruction and data addresses are always full 32-bit values. When an MMU is present, the BADDR field contains the virtual address.
If there is no MMU or MPU and the Nios II address space is less than 32 bits, unused high-order bits are written and read as zero. If there is no MMU, bit 31 of a data address (used to bypass the data cache) is always zero in the BADDR field.
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