Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

3.4.2.11. The badaddr Register

Nios® II/f processor provides information useful to system software for exception processing in the exception and badaddr registers when an exception occurs.

Note: The exception register is not available for Nios® II/e core, therefore you cannot add a MMU or MPU to the processor configuration. For more information, refer to the Nios® II Core Implementation Details chapter of this document.

When an exception occurs in Nios® II/f processor, the badaddr register contains the byte instruction or data address associated with certain exceptions at the time the exception occurred. The Nios® II Exceptions Table lists which exceptions write the badaddr register along with the value written.

Table 23.  badaddr Control Register Fields
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BADDR
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BADDR
Table 24.  badaddr Control Register Field Descriptions
Field Description Access Reset Available
BADDR BADDR contains the byte instruction address or data address associated with an exception when certain exceptions occur. The Address column of the Nios® II Exceptions Table lists which exceptions write the BADDR field. Read 0 Only with Nios® II/f

The BADDR field allows up to a 32-bit instruction address or data address. If an MMU or MPU is present, the BADDR field is 32 bits because MMU and MPU instruction and data addresses are always full 32-bit values. When an MMU is present, the BADDR field contains the virtual address.

If there is no MMU or MPU and the Nios II address space is less than 32 bits, unused high-order bits are written and read as zero. If there is no MMU, bit 31 of a data address (used to bypass the data cache) is always zero in the BADDR field.

Did you find the information on this page useful?

Characters remaining:

Feedback Message