Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

3.7.7.9. Misaligned Destination Address

The Nios® II processor can check for misaligned destination addresses of the callr, jmp, ret, eret, bret, and all branch instructions and generate an exception when a misaligned destination address is encountered. When your system contains an MMU or MPU, misaligned destination address checking is always on. When no MMU or MPU is present, you have the option to have the processor check for misaligned destination addresses.

For information about controlling this option, refer to the Instantiating the Nios® II Processor chapter of the Nios® II Processor Reference Handbook.

A destination address is considered misaligned if the target byte address of the instruction is not a multiple of four.

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