Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

5.3.5. Execution Pipeline

This section provides an overview of the pipeline behavior for the benefit of performance-critical applications. Designers can use this information to minimize unnecessary processor stalling. Most application programmers never need to analyze the performance of individual instructions.

The Nios II/s core employs a 5-stage pipeline.

Table 70.  Implementation Pipeline Stages for Nios II/s Core
Stage Letter Stage Name
F Fetch
D Decode
E Execute
M Memory
W Writeback

Up to one instruction is dispatched or retired per cycle. Instructions are dispatched and retired in-order. Static branch prediction is implemented using the branch offset direction; a negative offset (backward branch) is predicted as taken, and a positive offset (forward branch) is predicted as not taken. The pipeline stalls for the following conditions:

  • Multi-cycle instructions (e.g., shift/rotate without hardware multiply)
  • Avalon® -MM instruction master port read accesses
  • Avalon® -MM data master port read/write accesses
  • Data dependencies on long latency instructions (for example: load, multiply, shift operations)

Did you find the information on this page useful?

Characters remaining:

Feedback Message