5.3.5. Execution Pipeline
The Nios II/s core employs a 5-stage pipeline.
|Stage Letter||Stage Name|
Up to one instruction is dispatched or retired per cycle. Instructions are dispatched and retired in-order. Static branch prediction is implemented using the branch offset direction; a negative offset (backward branch) is predicted as taken, and a positive offset (forward branch) is predicted as not taken. The pipeline stalls for the following conditions:
- Multi-cycle instructions (e.g., shift/rotate without hardware multiply)
- Avalon® -MM instruction master port read accesses
- Avalon® -MM data master port read/write accesses
- Data dependencies on long latency instructions (for example: load, multiply, shift operations)
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