Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

3.7.7. Instruction-Related Exceptions

Instruction-related exceptions occur during execution of Nios II instructions. When they occur, the processor perform the steps outlined in the "Exception Processing Flow" section of this chapter.

The Nios® II processor generates the following instruction-related exceptions:

  • Trap instruction
  • Break instruction
  • Unimplemented instruction
  • Illegal instruction
  • Supervisor-only instruction
  • Supervisor-only instruction address
  • Supervisor-only data address
  • Misaligned data address
  • Misaligned destination address
  • Division error
  • Fast TLB miss
  • Double TLB miss
  • TLB permission violation
  • MPU region violation
Note: All noninterrupt exception handlers must run in the normal register set.

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