Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

3.7.7.12. Double TLB Miss

Double TLB miss exceptions are implemented only in Nios® II processors that include the MMU. When a TLB miss exception occurs while software is currently processing an exception (that is, when status.EH = 1), a double TLB miss exception is generated. Specifically, whenever the processor cannot find a TLB entry matching the VPN (optionally extended by a process identifier) and status.EH = 1, the result is a double TLB miss exception. The most common scenario is that a double TLB miss exception occurs during processing of a fast TLB miss exception. The processor preserves register values from the original exception and transfers control to the general exception handler which processes the newly-generated exception.

There are two kinds of double TLB miss exceptions:

  • Double TLB miss (instruction)—Any instruction fetch can cause this exception.
  • Double TLB miss (data)—Load, store, initda, and flushda instructions can cause this exception.

The general exception handler can inspect either the exception.CAUSE or tlbmisc.D field to determine which kind of double TLB miss exception occurred.

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