Nios® II Processor Reference Guide

ID 683836
Date 8/28/2023
Document Table of Contents

3.5.2. MPU Initialization

Your system software must provide a data structure that contains the region information described in the "Memory Regions" section of this chapter for each active thread. The data structure ideally contains two 32-bit values that correspond to the mpubase and mpuacc register formats.

The MPU is disabled on system reset. Before enabling the MPU, Intel FPGA recommends initializing all MPU regions. Enable desired instruction and data regions by writing each region’s attributes to the mpubase and mpuacc registers as described in the "MPU Region Read and Write Operations" section of this chapter. You must also disable unused regions. When using region size, clear mpuacc.MASK to zero. When using limit, set the mpubase.BASE to a nonzero value and clear mpuacc.LIMIT to zero.

Note: You must enable at least one instruction and one data region, otherwise unpredictable behavior might occur.

To perform a context switch, use a wrctl to write a zero to the PE field of the config register to disable the MPU, define all MPU regions from the new thread’s data structure, and then use another wrctl to write a one to config.PE to enable the MPU.

Define each region using the pair of wrctl instructions described in the "MPU Region Read and Write Operations" section of this chapter. Repeat this dual wrctl instruction sequence until all desired regions are defined.

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