Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

3.4.2.10. The tlbmisc Register

The tlbmisc register contains the remaining TLB-related fields and is only available in systems with an MMU.
Table 21.  tlbmisc Control Register Fields
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved EE WAY RD WE PID
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PID DBL BAD PERM D
Table 22.  tlbmisc Control Register Field Descriptions
Field Description Access Reset Available
EE If this field is a 1, a software-triggered ECC error (1, 2, or 3 bit error) occurred because software initiated a TLB read operation. Only set this field to 1 if CONFIG.ECCEN is 1. Read/Write 0 Only with MMU and EEC
WAY The WAY field controls the mapping from the VPN to a particular TLB entry.

This field size is variable. Unused upper bits must be written as zero.

Read/Write 0 Only with MMU
RD RD is the read flag. Setting RD to one triggers a TLB read operation. Write 0 Only with MMU
WE WE is the TLB write enable flag. When WE = 1, a write to tlbacc writes through to a TLB entry. Read/Write 0 Only with MMU
PID PID is the process identifier field.

This field size is variable. Unused upper bits must be written as zero.

Read/Write 0 Only with MMU
DBL DBL is the double TLB miss exception flag. Read 0 Only with MMU
BAD BAD is the bad virtual address exception flag. Read 0 Only with MMU
PERM PERM is the TLB permission violation exception flag. Read 0 Only with MMU
D D is the data access exception flag. When D = 1, the exception is a data access exception. When D = 0, the exception is an instruction access exception. Read 0 Only with MMU

For DBL, BAD, and PERM fields you can also use exception.CAUSE to determine these exceptions.

The following sections provide more information about the tlbmisc fields.

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