Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

2.6.6. Memory Protection Unit

The optional Nios II MPU provides the following features and functionality:
  • Memory protection
  • Up to 32 instruction regions and 32 data regions
  • Variable instruction and data region sizes
  • Amount of region memory defined by size or upper address limit
  • Read and write access permissions for data regions
  • Execute access permissions for instruction regions
  • Overlapping regions

For more information about the MPU implementation, refer to the Programming Model chapter of the Nios® II Processor Reference Handbook.

You can optionally include the MPU when you instantiate the Nios® II processor in your Nios® II hardware system. When present, the MPU is always enabled. Several parameters are available, allowing you to optimize the MPU for your system needs.

For complete details about user-selectable parameters for the Nios II MPU, refer to the Instantiating the Nios® II Processor chapter of the Nios® II Processor Reference Handbook.

Note: The Nios II MPU is optional and mutually exclusive from the Nios II MMU. Nios® II systems can include either an MPU or MMU, but cannot include both an MPU and MMU on the same Nios® II processor core.

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