2.6.6. Memory Protection Unit
- Memory protection
- Up to 32 instruction regions and 32 data regions
- Variable instruction and data region sizes
- Amount of region memory defined by size or upper address limit
- Read and write access permissions for data regions
- Execute access permissions for instruction regions
- Overlapping regions
For more information about the MPU implementation, refer to the Programming Model chapter of the Nios® II Processor Reference Handbook.
You can optionally include the MPU when you instantiate the Nios® II processor in your Nios® II hardware system. When present, the MPU is always enabled. Several parameters are available, allowing you to optimize the MPU for your system needs.
For complete details about user-selectable parameters for the Nios II MPU, refer to the Instantiating the Nios® II Processor chapter of the Nios® II Processor Reference Handbook.
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