Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

3.7.11. Handling Nested Exceptions

The Nios® II processor supports several types of nested exceptions, depending on which optional features are implemented. Nested exceptions can occur under the following circumstances:
  • An exception handler enables maskable interrupts
  • An EIC is present, and an NMI occurs
  • An EIC is present, and the processor is configured to keep maskable interrupts enabled when taking an interrupt
  • An exception handler triggers an instruction-related exception

    For details about when the Nios® II processor takes exceptions, refer to “Exception Processing Flow” on page 3–44.

For details about unimplemented instructions, refer to the Processor Architecture chapter of the Nios® II Processor Reference Handbook.

For details about MMU and MPU exceptions, refer to the Instruction-Related Exceptions section of this chapter.

A system can be designed to eliminate the possibility of nested exceptions. However, if nested exceptions are possible, the exception handlers must be carefully written to prevent each handler from corrupting the context in which a pre-empted handler runs.

If an exception handler issues a trap instruction, an optional instruction, or an instruction which could generate an MMU or MPU exception, it must save and restore the contents of the estatus and ea registers.

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