Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

5.4.3. Memory Access

The Nios II/e core does not provide instruction cache or data cache. All memory and peripheral accesses generate an Avalon® -MM transfer. The Nios II/e core can address up to 4 GB of external memory, full 32-bit addressing.

For information regarding data cache bypass methods, refer to the Processor Architecture chapter of the Nios® II Processor Reference Handbook.

The Nios II/e core does not provide instruction cache or data cache. All memory and peripheral accesses generate an Avalon® -MM transfer.

For information regarding data cache bypass methods, refer to the Processor Architecture chapter of the Nios® II Processor Reference Handbook.

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