Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

5.2.7. Execution Pipeline

This section provides an overview of the pipeline behavior for the benefit of performance-critical applications. Designers can use this information to minimize unnecessary processor stalling. Most application programmers never need to analyze the performance of individual instructions.

The Nios II/f core employs a 6-stage pipeline.

Table 64.  Implementation Pipeline Stages for Nios II/f Core
Stage Letter Stage Name
F Fetch
D Decode
E Execute
M Memory
A Align
W Writeback

Up to one instruction is dispatched or retired per cycle. Instructions are dispatched and retired in order. Dynamic branch prediction is implemented using a 2-bit branch history table. The pipeline stalls for the following conditions:

  • Multi-cycle instructions
  • Avalon® -MM instruction master port read accesses
  • Avalon® -MM data master port read/write accesses
  • Data dependencies on long latency instructions (for example: load, multiply, shift).

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