5.2.7. Execution Pipeline
The Nios II/f core employs a 6-stage pipeline.
|Stage Letter||Stage Name|
Up to one instruction is dispatched or retired per cycle. Instructions are dispatched and retired in order. Dynamic branch prediction is implemented using a 2-bit branch history table. The pipeline stalls for the following conditions:
- Multi-cycle instructions
- Avalon® -MM instruction master port read accesses
- Avalon® -MM data master port read/write accesses
- Data dependencies on long latency instructions (for example: load, multiply, shift).
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