Nios® II Processor Reference Guide

ID 683836
Date 8/28/2023
Document Table of Contents Pipeline Stalls

The pipeline is set up so that if a stage stalls, no new values enter that stage or any earlier stages. No “catching up” of pipeline stages is allowed, even if a pipeline stage is empty.

Only the A-stage and D-stage are allowed to create stalls.

The A-stage stall occurs if any of the following conditions occurs:

  • An A-stage memory instruction is waiting for Avalon® -MM data master requests to complete. Typically this happens when a load or store misses in the data cache, or a flushd instruction needs to write back a dirty line.
  • An A-stage shift/rotate instruction is still performing its operation. This only occurs with the multicycle shift circuitry (i.e., when the hardware multiplier is not available).
  • An A-stage divide instruction is still performing its operation. This only occurs when the optional divide circuitry is available.
  • An A-stage multicycle custom instruction is asserting its stall signal. This only occurs if the design includes multicycle custom instructions.

The D-stage stall occurs if an instruction is trying to use the result of a late result instruction too early and no M-stage pipeline flush is active. The late result instructions are loads, shifts, rotates, rdctl, multiplies (if hardware multiply is supported), divides (if hardware divide is supported), and multicycle custom instructions (if present).