126.96.36.199. The status Register
|RSIE||RSIE is the register set interrupt-enable bit. When set to 1, this bit allows the processor to service external interrupts requesting the register set that is currently in use. When set to 0, this bit disallows servicing of such interrupts.||Read/Write||1||EIC interface and shadow register sets only1|
|NMI||NMI is the nonmaskable interrupt mode bit. The processor sets NMI to 1 when it takes a nonmaskable interrupt.||Read||0||EIC interface only4|
|PRS|| PRS is the previous register set field. The processor copies the CRS field to the PRS field upon one of the following events:
||Read/Write||0||Shadow register sets only4|
|CRS|| CRS is the current register set field. CRS indicates which register set is currently in use. Register set 0 is the normal register set, while register sets 1 and higher are shadow register sets. The processor sets CRS to zero on any noninterrupt exception.
The number of significant bits in the CRS and PRS fields depends on the number of shadow register sets implemented in the Nios II core. Unused high-order bits are always read as 0, and must be written as 0.
|Read2||0||Shadow register sets only4|
|IL||IL is the interrupt level field. The IL field controls what level of external maskable interrupts can be serviced. The processor services a maskable interrupt only if its requested interrupt level is greater than IL.||Read/Write||0||EIC interface only4|
|IH||IH is the interrupt handler mode bit. The processor sets IH to one when it takes an external interrupt.||Read/Write||0||EIC interface only4|
|EH 3||EH is the exception handler mode bit. The processor sets EH to one when an exception occurs (including breaks). Software clears EH to zero when ready to handle exceptions again. EH is used by the MMU to determine whether a TLB miss exception is a fast TLB miss or a double TLB miss. In systems without an MMU, EH is always zero.||Read/Write||0||MMU or ECC only4|
|U 3||U is the user mode bit. When U = 1, the processor operates in user mode. When U = 0, the processor operates in supervisor mode. In systems without an MMU, U is always zero.||Read/Write||0||MMU or MPU only4|
|PIE||PIE is the processor interrupt-enable bit. When PIE = 0, internal and maskable external interrupts and noninterrupt exceptions are ignored. When PIE = 1, internal and maskable external interrupts can be taken, depending on the status of the interrupt controller. Noninterrupt exceptions are unaffected by PIE.||Read/Write||0||Always|
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