Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

3.4.2.1. The status Register

The value in the status register determines the state of the Nios® II processor. All status bits are set to predefined values at processor reset. Some bits are exclusively used by and available only to certain features of the processor, such as the MMU, MPU or external interrupt controller (EIC) interface.
Table 11.  status Control Register Fields
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved RSIE NMI PRS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRS IL IH EH U PIE
Table 12.  status Control Register Field Descriptions
Bit Description Access Reset Available
RSIE RSIE is the register set interrupt-enable bit. When set to 1, this bit allows the processor to service external interrupts requesting the register set that is currently in use. When set to 0, this bit disallows servicing of such interrupts. Read/Write 1 EIC interface and shadow register sets only1
NMI NMI is the nonmaskable interrupt mode bit. The processor sets NMI to 1 when it takes a nonmaskable interrupt. Read 0 EIC interface only4
PRS PRS is the previous register set field. The processor copies the CRS field to the PRS field upon one of the following events:
  • In a processor with no MMU, on any exception
  • In a processor with an MMU, on one of the following:

    Break exception

    Nonbreak exception when status.EH is zero

    The processor copies CRS to PRS immediately after copying the status register to estatus, bstatus or sstatus.

    The number of significant bits in the CRS and PRS fields depends on the number of shadow register sets implemented in the Nios II core. The value of CRS and PRS can range from 0 to n-1, where n is the number of implemented register sets. The processor core implements the number of significant bits needed to represent n-1. Unused high-order bits are always read as 0, and must be written as 0.

    1 Ensure that system software writes only valid register set numbers to the PRS field. Processor behavior is undefined with an unimplemented register set number.

Read/Write 0 Shadow register sets only4
CRS CRS is the current register set field. CRS indicates which register set is currently in use. Register set 0 is the normal register set, while register sets 1 and higher are shadow register sets. The processor sets CRS to zero on any noninterrupt exception.

The number of significant bits in the CRS and PRS fields depends on the number of shadow register sets implemented in the Nios II core. Unused high-order bits are always read as 0, and must be written as 0.

Read2 0 Shadow register sets only4
IL IL is the interrupt level field. The IL field controls what level of external maskable interrupts can be serviced. The processor services a maskable interrupt only if its requested interrupt level is greater than IL. Read/Write 0 EIC interface only4
IH IH is the interrupt handler mode bit. The processor sets IH to one when it takes an external interrupt. Read/Write 0 EIC interface only4
EH 3 EH is the exception handler mode bit. The processor sets EH to one when an exception occurs (including breaks). Software clears EH to zero when ready to handle exceptions again. EH is used by the MMU to determine whether a TLB miss exception is a fast TLB miss or a double TLB miss. In systems without an MMU, EH is always zero. Read/Write 0 MMU or ECC only4
U 3 U is the user mode bit. When U = 1, the processor operates in user mode. When U = 0, the processor operates in supervisor mode. In systems without an MMU, U is always zero. Read/Write 0 MMU or MPU only4
PIE PIE is the processor interrupt-enable bit. When PIE = 0, internal and maskable external interrupts and noninterrupt exceptions are ignored. When PIE = 1, internal and maskable external interrupts can be taken, depending on the status of the interrupt controller. Noninterrupt exceptions are unaffected by PIE. Read/Write 0 Always
1 When this field is unimplemented, the field value always reads as 1, and the processor behaves accordingly.
2 The CRS field is read-only. For information about manually changing register sets, refer to the External Interrupt Controller Interface section.
3 The state where both EH and U are one is illegal and causes undefined results.
4 When this field is unimplemented, the field value always reads as 0, and the processor behaves accordingly.

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