3.4.2.1. The status Register
3.4.2.2. The estatus Register
3.4.2.3. The bstatus Register
3.4.2.4. The ienable Register
3.4.2.5. The ipending Register
3.4.2.6. The cpuid Register
3.4.2.7. The exception Register
3.4.2.8. The pteaddr Register
3.4.2.9. The tlbacc Register
3.4.2.10. The tlbmisc Register
3.4.2.11. The badaddr Register
3.4.2.12. The config Register
3.4.2.13. The mpubase Register
3.4.2.14. The mpuacc Register
3.6.3.1. Instruction Cache Tag RAM
3.6.3.2. Instruction Cache Data RAM
3.6.3.3. ITCMs
3.6.3.4. Register File RAM Blocks
3.6.3.5. Data Cache Tag RAM
3.6.3.6. Data Cache Data RAM (Clean Line)
3.6.3.7. Data Cache Data RAM (Dirty Line)
3.6.3.8. Data Cache Victim Line Buffer RAM
3.6.3.9. DTCMs
3.6.3.10. MMU TLB RAM
3.7.1. Terminology
3.7.2. Exception Overview
3.7.3. Exception Latency
3.7.4. Reset Exceptions
3.7.5. Break Exceptions
3.7.6. Interrupt Exceptions
3.7.7. Instruction-Related Exceptions
3.7.8. Other Exceptions
3.7.9. Exception Processing Flow
3.7.10. Determining the Cause of Interrupt and Instruction-Related Exceptions
3.7.11. Handling Nested Exceptions
3.7.12. Handling Nonmaskable Interrupts
3.7.13. Masking and Disabling Exceptions
3.7.7.1. Trap Instruction
3.7.7.2. Break Instruction
3.7.7.3. Unimplemented Instruction
3.7.7.4. Illegal Instruction
3.7.7.5. Supervisor-Only Instruction
3.7.7.6. Supervisor-Only Instruction Address
3.7.7.7. Supervisor-Only Data Address
3.7.7.8. Misaligned Data Address
3.7.7.9. Misaligned Destination Address
3.7.7.10. Division Error
3.7.7.11. Fast TLB Miss
3.7.7.12. Double TLB Miss
3.7.7.13. TLB Permission Violation
3.7.7.14. MPU Region Violation
3.9.1. Data Transfer Instructions
3.9.2. Arithmetic and Logical Instructions
3.9.3. Move Instructions
3.9.4. Comparison Instructions
3.9.5. Shift and Rotate Instructions
3.9.6. Program Control Instructions
3.9.7. Other Control Instructions
3.9.8. Custom Instructions
3.9.9. No-Operation Instruction
3.9.10. Potential Unimplemented Instructions
8.5.1. add
8.5.2. addi
8.5.3. and
8.5.4. andhi
8.5.5. andi
8.5.6. beq
8.5.7. bge
8.5.8. bgeu
8.5.9. bgt
8.5.10. bgtu
8.5.11. ble
8.5.12. bleu
8.5.13. blt
8.5.14. bltu
8.5.15. bne
8.5.16. br
8.5.17. break
8.5.18. bret
8.5.19. call
8.5.20. callr
8.5.21. cmpeq
8.5.22. cmpeqi
8.5.23. cmpge
8.5.24. cmpgei
8.5.25. cmpgeu
8.5.26. cmpgeui
8.5.27. cmpgt
8.5.28. cmpgti
8.5.29. cmpgtu
8.5.30. cmpgtui
8.5.31. cmple
8.5.32. cmplei
8.5.33. cmpleu
8.5.34. cmpleui
8.5.35. cmplt
8.5.36. cmplti
8.5.37. cmpltu
8.5.38. cmpltui
8.5.39. cmpne
8.5.40. cmpnei
8.5.41. custom
8.5.42. div
8.5.43. divu
8.5.44. eret
8.5.45. flushd
8.5.46. flushda
8.5.47. flushi
8.5.48. flushp
8.5.49. initd
8.5.50. initda
8.5.51. initi
8.5.52. jmp
8.5.53. jmpi
8.5.54. ldb / ldbio
8.5.55. ldbu / ldbuio
8.5.56. ldh / ldhio
8.5.57. ldhu / ldhuio
8.5.58. ldw / ldwio
8.5.59. mov
8.5.60. movhi
8.5.61. movi
8.5.62. movia
8.5.63. movui
8.5.64. mul
8.5.65. muli
8.5.66. mulxss
8.5.67. mulxsu
8.5.68. mulxuu
8.5.69. nextpc
8.5.70. nop
8.5.71. nor
8.5.72. or
8.5.73. orhi
8.5.74. ori
8.5.75. rdctl
8.5.76. rdprs
8.5.77. ret
8.5.78. rol
8.5.79. roli
8.5.80. ror
8.5.81. sll
8.5.82. slli
8.5.83. sra
8.5.84. srai
8.5.85. srl
8.5.86. srli
8.5.87. stb / stbio l
8.5.88. sth / sthio
8.5.89. stw / stwio
8.5.90. sub
8.5.91. subi
8.5.92. sync
8.5.93. trap
8.5.94. wrctl
8.5.95. wrprs
8.5.96. xor
8.5.97. xorhi
8.5.98. xori
2.6.5. Memory Management Unit
The optional Nios II MMU provides the following features and functionality:
- Virtual to physical address mapping
- Memory protection
- 32-bit virtual and physical addresses, mapping a 4-GB virtual address space into as much as 4 GB of physical memory
- 4-KB page and frame size
- Low 512 MB of physical address space available for direct access
- Hardware translation lookaside buffers (TLBs), accelerating address translation
- Separate TLBs for instruction and data accesses
- Read, write, and execute permissions controlled per page
- Default caching behavior controlled per page
- TLBs acting as n-way set-associative caches for software page tables
- TLB sizes and associativities configurable in the Nios® II Processor parameter editor
- Format of page tables (or equivalent data structures) determined by system software
- Replacement policy for TLB entries determined by system software
- Write policy for TLB entries determined by system software
For more information about the MMU implementation, refer to the Programming Model chapter of the Nios® II Processor Reference Handbook.
You can optionally include the MMU when you instantiate the Nios® II processor in your Nios® II hardware system. When present, the MMU is always enabled, and the data and instruction caches are virtually-indexed, physically-tagged caches. Several parameters are available, allowing you to optimize the MMU for your system needs.
For complete details about user-selectable parameters for the Nios II MMU, refer to the Instantiating the Nios® II Processor chapter of the Nios® II Processor Reference Handbook.
Note: The Nios II MMU is optional and mutually exclusive from the Nios II MPU. Nios® II systems can include either an MMU or MPU, but cannot include both an MMU and MPU on the same Nios® II processor core.
Related Information