Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

2.6.5. Memory Management Unit

The optional Nios II MMU provides the following features and functionality:
  • Virtual to physical address mapping
  • Memory protection
  • 32-bit virtual and physical addresses, mapping a 4-GB virtual address space into as much as 4 GB of physical memory
  • 4-KB page and frame size
  • Low 512 MB of physical address space available for direct access
  • Hardware translation lookaside buffers (TLBs), accelerating address translation
    • Separate TLBs for instruction and data accesses
    • Read, write, and execute permissions controlled per page
    • Default caching behavior controlled per page
    • TLBs acting as n-way set-associative caches for software page tables
    • TLB sizes and associativities configurable in the Nios® II Processor parameter editor
  • Format of page tables (or equivalent data structures) determined by system software
  • Replacement policy for TLB entries determined by system software
  • Write policy for TLB entries determined by system software

For more information about the MMU implementation, refer to the Programming Model chapter of the Nios® II Processor Reference Handbook.

You can optionally include the MMU when you instantiate the Nios® II processor in your Nios® II hardware system. When present, the MMU is always enabled, and the data and instruction caches are virtually-indexed, physically-tagged caches. Several parameters are available, allowing you to optimize the MMU for your system needs.

For complete details about user-selectable parameters for the Nios II MMU, refer to the Instantiating the Nios® II Processor chapter of the Nios® II Processor Reference Handbook.

Note: The Nios II MMU is optional and mutually exclusive from the Nios II MPU. Nios® II systems can include either an MMU or MPU, but cannot include both an MMU and MPU on the same Nios® II processor core.

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