Nios® II Processor Reference Guide

ID 683836
Date 8/28/2023
Document Table of Contents

2.5.2. EIC Interface

An EIC provides high performance hardware interrupts to reduce your program's interrupt latency. An EIC is typically used in conjunction with shadow register sets and when you need more than the 32 interrupts provided by the Nios II internal interrupt controller.

The Nios® II processor connects to an EIC through the EIC interface. When an EIC is present, the internal interrupt controller is not implemented; Platform Designer connects interrupts to the EIC.

The EIC selects among active interrupts and presents one interrupt to the Nios® II processor, with interrupt handler address and register set selection information. The interrupt selection algorithm is specific to the EIC implementation, and is typically based on interrupt priorities. The Nios® II processor does not depend on any specific interrupt prioritization scheme in the EIC.

For every external interrupt, the EIC presents an interrupt level. The Nios® II processor uses the interrupt level in determining when to service the interrupt.

Any external interrupt can be configured as an NMI. NMIs are not masked by the status.PIE bit, and have no interrupt level.

An EIC can be software-configurable.

Note: When the EIC interface and shadow register sets are implemented on the Nios II core, you must ensure that your software is built with the Nios II EDS version 9.0 or higher. Earlier versions have an implementation of the eret instruction that is incompatible with shadow register sets.

For a typical example of an EIC, refer to the Vectored Interrupt Controller chapter in the Embedded Peripherals IP User Guide.

For details about EIC usage, refer to “Exception Processing” in the Programming Model chapter of the Nios® II Processor Reference Handbook.

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