Nios® II Processor Reference Guide

ID 683836
Date 8/28/2023
Document Table of Contents

3.2.4. TLB Organization

A TLB functions as a cache for the operating system’s page table. In Nios® II processors with an MMU, one main TLB is shared by instruction and data accesses. The TLB is stored in on-chip RAM and handles translations for instruction fetches and instructions that perform data accesses.

The TLB is organized as an n-way set-associative cache. The software specifies the way (set) when loading a new entry.

Note: You can configure the number of TLB entries and the number of ways (set associativity) of the TLB with the Nios® II Processor parameter editor in Platform Designer. By default, the TLB is a 16-way cache. The default number of entries depends on the target device, as follows:
  • Cyclone III®, Stratix III®, Stratix IV—256 entries, requiring one M9K RAM

    For more information, refer to the Instantiating the Nios® II Processor chapter of the Nios® II Processor Reference Handbook.

The operating system software is responsible for guaranteeing that multiple TLB entries do not map the same virtual address. The hardware behavior is undefined when multiple entries map the same virtual address.

Each TLB entry consists of a tag and data portion. This is analogous to the tag and data portion of instruction and data caches.

Refer to the Nios II Core Implementation Details chapter of the Nios® II Processor Reference Handbook for information about instruction and data caches.

The tag portion of a TLB entry contains information used when matching a virtual address to a TLB entry.

Table 7.  TLB Tag Portion Contents
Field Name Description
VPN VPN is the virtual page number field. This field is compared with the top 20 bits of the virtual address.
PID PID is the process identifier field. This field is compared with the value of the current process identifier stored in the tlbmisc control register, effectively extending the virtual address. The field size is configurable in the Nios_II Processor parameter editor, and can be between 8 and 14 bits.
G G is the global flag. When G = 1, the PID is ignored in the TLB lookup.

The TLB data portion determines how to translate a matching virtual address to a physical address.

Table 8.  TLB Data Portion Contents
Field Name Description
PFN PFN is the physical frame number field. This field specifies the upper bits of the physical address. The size of this field depends on the range of physical addresses present in the system. The maximum size is 20 bits.
C C is the cacheable flag. Determines the default data cacheability of a page. Can be overridden for data accesses using I/O load and store family of Nios II instructions.
R R is the readable flag. Allows load instructions to read a page.
W W is the writable flag. Allows store instructions to write a page.
X X is the executable flag. Allows instruction fetches from a page.
Note: Because there is no “valid bit” in the TLB entry, the operating system software invalidates the TLB by writing unique VPN values from the I/O partition of virtual addresses into each TLB entry.