Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

3.7.2. Exception Overview

Each of the Nios II exceptions falls into one of the following categories:

  • Reset exception—Occurs when the Nios® II processor is reset. Control is transferred to the reset address you specify in the Nios® II processor IP core setup parameters.
  • Break exception—Occurs when the JTAG debug module requests control. Control is transferred to the break address you specify in the Nios® II processor IP core setup parameters.
  • Interrupt exception—Occurs when a peripheral device signals a condition requiring service
  • Instruction-related exception—Occurs when any of several internal conditions occurs, as detailed in the Nios® II Exceptions Table. Control is transferred to the exception address you specify in the Nios® II processor IP core setup parameters.

The following table columns specify information for the exceptions:

  • Exception—Gives the name of the exception.
  • Type—Specifies the exception type.
  • Available—Specifies when support for that exception is present.
  • Cause—Specifies the value of the CAUSE field of the exception register, for exceptions that write the exception.CAUSE field.
  • Address—Specifies the instruction or data address associated with the exception.
  • Vector—Specifies which exception vector address the processor passes control to when the exception occurs.
Table 39.  Nios II Exceptions (In Decreasing Priority Order)
Exception Type Available Cause Address Vector
Reset Reset Always 0   Reset
Hardware break Break Always   Break
Processor-only reset request Reset Always 1   Reset
ECC Data Cache Writeback Error Instruction-related ECC and data cache 22   General exception
Internal interrupt Interrupt Internal interrupt controller 2 ea–4 11 General exception
External nonmaskable interrupt Interrupt External interrupt controller interface ea–4 11 Requested handler address 12
External maskable interrupt Interrupt External interrupt controller interface 2 ea–4 11 Requested handler address 12
ECC TLB error (instruction) Instruction-related MMU and ECC 18 ea–4 11 General exception
Supervisor-only instruction address 10 Instruction-related MMU 9 ea–4 11 General exception
Fast TLB miss (instruction)10  Instruction-related MMU 12 pteaddr.VPN, ea–4 11 Fast TLB Miss exception
Double TLB miss (instruction) 10 Instruction-related MMU 12 pteaddr.VPN, ea–4 11 General exception
TLB permission violation (execute) 10 Instruction-related MMU 13 pteaddr.VPN, ea–4 11 General exception
ECC register file error Instruction-related ECC 20 ea–4 11 General exception
MPU region violation (instruction) 10 Instruction-related MPU 16 ea–4 11 General exception
ECC Fetch Error (instruction fetch)   ECC and ITCM 19 ea–4 11 General exception
ECC Register File Error   ECC 20 ea–4 11 General exception
Supervisor-only instruction Instruction-related MMU or MPU 10 ea–4 11 General exception
Trap instruction Instruction-related Always 3 ea–4 11 General exception
Illegal instruction Instruction-related Illegal instruction detection on, MMU, or MPU 5 ea–4 11 General exception
Unimplemented instruction Instruction-related Always 4 ea–4 11 General exception
Break instruction Instruction-related Always ba–4 11 Break
Supervisor-only data address Instruction-related MMU 11 badaddr (data address) General exception
Misaligned data address Instruction-related Illegal memory access detection on, MMU, or MPU 6 badaddr (data address) General exception
Misaligned destination address Instruction-related Illegal memory access detection on, MMU, or MPU 7 badaddr (destination address) General exception
ECC TLB error (data) Instruction-related MMU and ECC 18 badaddr (data address) General exception
Division error Instruction-related Division error detection on 8 ea–4 11 General exception
Fast TLB miss (data) Instruction-related MMU 12 pteaddr.VPN, badaddr (data address) Fast TLB Miss exception
Double TLB miss (data) Instruction-related MMU 12 pteaddr.VPN, badaddr (data address) General exception
TLB permission violation (read) Instruction-related MMU 14 pteaddr.VPN, badaddr (data address) General exception
TLB permission violation (write) Instruction-related MMU 15 pteaddr.VPN, badaddr (data address) General exception
MPU region violation (data) Instruction-related MPU 17 badaddr (data address) General exception
ECC Data Error   ECC and (data cache OR DTCM) 21 badaddr (data address) General exception
10 It is possible for any instruction fetch to cause this exception.
11 Refer to the Nios® II General-Purpose Registers Table for descriptions of the ea and ba registers.
12 For a description of the requested handler address, refer to the Requested Handler Address section of this chapter.

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