External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

12.2. Testing the EMIF Interface Using the Traffic Generator 2.0

The EMIF Configurable Traffic Generator 2.0 can assist in debugging and stress-testing your external memory interface. The traffic generator 2.0 supports Arria 10 and later device families.

Key Features

The traffic generator 2.0 has the following key features:

  • Is a standalone, soft-logic device that resides in the FPGA core.
  • Is independent of the FPGA architecture and the external memory protocol in use.
  • Offers configuration options for the generation of reads and writes, addressing, data, and data mask.

For information on using the Traffic Generator 2.0 from within the EMIF Debug Toolkit, refer to Traffic Generator 2.0 in External Memory Interface Debug Toolkit.

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