12.2. Testing the EMIF Interface Using the Traffic Generator 2.0
The traffic generator 2.0 has the following key features:
- Is a standalone, soft-logic device that resides in the FPGA core.
- Is independent of the FPGA architecture and the external memory protocol in use.
- Offers configuration options for the generation of reads and writes, addressing, data, and data mask.
For information on using the Traffic Generator 2.0 from within the EMIF Debug Toolkit, refer to Traffic Generator 2.0 in External Memory Interface Debug Toolkit.
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