12.2.2. Performing Your Own Tests Using Traffic Generator 2.0
The general flow of a configuration test stage, including the default test stages, is as follows:
- Configure the number of loops to be completed by the traffic generator (TG_LOOP_COUNT).
- Configure the number of writes and reads to be complete per loop (TG_WRITE_COUNT and TG_READ_COUNT respectively).
- Choose the burst length of each write and read (TG_BURST_LENGTH).
- Select starting write address by writing to the lower and upper bits of the address register (TG_SEQ_START_ADDR_WR_L and TG_SEQ_START_ADDR_WR_H, respectively).
- Select write address generation mode (TG_ADDR_MODE_WR).
- Select starting read address by writing to the lower and upper bits of the address register (TG_SEQ_START_ADDR_RD_L and TG_SEQ_START_ADDR_RD_H, respectively).
- Select read address generation mode (TG_ADDR_MODE_RD).
- If applicable, select sequential address increment (TG_SEQ_ADDR_INCR).
- Write initial values/seeds to the data and byte-enable generators (TG_DATA_SEED and TG_BYTEEN_SEED).
- Select generation mode of the data and byte-enable generators (TG_DATA_MODE and TG_BYTEEN_MODE).
- Initiate test (TG_START).
For a comprehensive example of how to write your own configuration test for simulation, refer to the test bench file, located at <example_design_directory>/sim/ed_sim/altera_emif_tg_avl_2_<>/sim/altera_emif_avl_tg_2_tb.sv
To iterate over the data generators or byte-enable generators, you must read the number of data generators and number of byte-enable generators. These values are mapped to read-accessible registers TG_NUM_DATA_GEN and TG_NUM_BYTEEN_GEN, respectively. The following example illustrates how one would configure the data generators to continuously output the pattern 0x5a, using the simulation test bench:
integer num_data_generators; … tg_send_cfg_read_0(TG_NUM_DATA_GEN, num_data_generators); tg_send_cfg_write_0(TG_DATA_MODE, 32'h1); for (i = 0; i < num_data_generators; i = i + 1) begin tg_send_cfg_write_0(TG_DATA_SEED + i, 32'h5A); end
Configuration test stages in hardware must be inserted into the RTL, and will resemble the single read/write, byte-enable, and block read/write stages in the default test pattern. In most cases, you can modify one of the existing stages to create the desired custom test stage. The stages are linear, finite, state machines that write predetermined values to the configuration address-mapped registers. As always, the last state in configuration is a write to address 0x0 or TG_START. The state machine then waits for the traffic generator to return a signal signifying its completion of the test stage.
Refer to the aforementioned default test stages as examples of hardware test stages. The default test stages are contained within the following files:
You can also configure the configurable traffic generator in real time using the EMIF Debug Toolkit. The configuration settings available in the Toolkit interface are detailed in the Configurable Traffic Generator 2.0 Configuration Options topic.
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