External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

12.2.1. Configurable Traffic Generator 2.0 Configuration Options

The EMIF Configurable Traffic Generator 2.0 offers a range of configuration options for fast debugging of your external memory interface. You configure the traffic generator by modifying address-mapped registers through the simulation test bench file or by creating a configuration test stage.

Configuration Syntax

The test bench includes an example test procedure.

The syntax for writing to a configuraton register is as follows:

tg_send_cfg_write_<index>(<Register Name>, <Value to be written>);

The index value represents the index of the memory interface (which is usually 0, but can be 0/1 in ping-pong PHY mode).

The register name values are listed in the tables of configuration options, and can also be found in the altera_emif_avl_tg_defs.sv file, in the same directory as the test bench.

The final configuration command must be a write of any value to TG_START, which starts the traffic generator for the specified interface.

Configuration Options

Configuration options are divided into read/write, address, data, and data mask generation categories.
Table 110.  Configuration Options for Read/Write Generation
Toolkit GUI Tab Toolkit GUI Parameter Register Name Description
-- -- TG_START Tells the system to perform a write to this register to initiate traffic generation test.
Loops Loops TG_LOOP_COUNT Specifies the number of read/write loops to perform before completion of the test stage. A loop is a single iteration of writes and reads. Upon completion, the base address is either incremented (SEQ or RAND_SEQ) or replaced by a newly generated random address (RAND or RAND_SEQ).
Writes per block TG_WRITE_COUNT Specifies the number of writes to be performed in each loop of the test.
Reads per block TG_READ_COUNT Specifies the number of reads to be performed in each loop of the test. This register must have the same value as TG_WRITE_COUNT.
-- TG_WRITE_REPEAT_COUNT Specifies the number of times each write transaction is repeated.
-- TG_READ_REPEAT_COUNT Specifies the number of times each read transaction is repeated.
Reads per block TG_BURST_LENGTH Configures the length of each write/read burst to memory.
-- -- TG_CLEAR_FIRST_FAIL Clears the record of first failure occurrence. New failure information such as expected data, read data, and fail address, is written to the corresponding registers following the next failure.
-- -- TG_TEST_BYTEEN Toggles the byte-enable (data mask enable) register within the traffic generator which allows the current test to use byte-enable signals.
-- -- TG_DATA_MODE Specifies the source of data used for data signal generation during the test. Set to 0 to use pseudo-random data. Set to 1 to use user-specified values stored in the static data generators.
-- -- TG_BYTEEN_MODE Specifies the source of data used for byte-enable signal generation during the test. Set to 0 to use pseudo-random data. Set to 1 to use user-specified values stored in the static data generators.
Table 111.  Configuration Options for Address Generation
Toolkit GUI Tab Toolkit GUI Parameter Register Name Description
Address Start Address TG_SEQ_START_ADDR_WR_L Specifies the sequential start address (lower 32 bits).
Start address TG_SEQ_START_ADDR_WR_H Specifies the sequential start address (upper 32 bits)
Address mode TG_ADDR_MODE_WR Specifies how write addresses are generated by writing the value in parentheses to the register address. Values are: randomize the address for every write (0), increment sequentially from a specified address (1), increment sequentially from a random address (2), or perform one hot addressing (3).
Number of sequential address TG_RAND_SEQ_ADDRS_WR Specifies the number of times to increment sequentially on the random base address before generating a new random write address.
Return to start address TG_RETURN_TO_START_ADDR Return to start address in deterministic sequential address mode (if 1 is written to TG_ADDR_MODE_WR) after every loop of transactions.
Rank | Mask Mode TG_RANK_MASK_EN Specifies the rank masking mode by writing the value in parentheses to the register address. Values are: disable rank masking (0), maintain a static rank mask (1), cycle through rank masks incrementally (2).
Bank Address | Mask Mode TG_BANK_MASK_EN Specifies the bank masking mode by writing the value in parentheses to the register address. Values are: disable bank masking (0), maintain a static bank mask (1), cycle through bank masks incrementally (2), cycle through only three consecutive bank masks (3).
Row | Mask Mode TG_ROW_MASK_EN Specifies the mode for row masking by writing the value in parentheses to the register address. Values are: disable row masking (0), maintain a static row mask (1), cycle through row masks incrementally (2).
Bank Group | Mask Mode TG_BG_MASK_EN Specifies the mode for bank group masking by writing the value in parentheses to the register address. Values are: disable bank group masking (0), maintain a static bank group mask (1), cycle through bank group masks incrementally (2).
Rank | Mask Value TG_RANK_MASK Specifies the initial rank to be masked into the generated traffic generator address.
Bank Address | Mask Value TG_BANK_MASK Specifies the initial bank to be masked into the generated traffic generator address.
Row | Mask Value TG_ROW_MASK Specifies the initial row to be masked into the generated traffic generator address.
Bank Group | Mask Value TG_BG_MASK Specifies the initial bank group to be masked into the generated traffic generator address.
Sequential Address Increment TG_SEQ_ADDR_INCR Specifies the increment to use when sequentially incrementing the address. This value is used by both deterministic sequential addressing and random sequential addressing. (Refer to TG_ADDR_MODE_WR)
Start Address TG_SEQ_START_ADDR_RD_L Specifies the sequential start read address (lower 32 bits).
TG_SEQ_START_ADDR_RD_H Specifies the sequential start read address (upper 32 bits).
Address Mode TG_ADDR_MODE_RD Similar to TG_ADDR_MODE_WR but for reads.
Number of sequential address TG_RAND_SEQ_ADDRS_RD Specifies the number of times to increment the random sequential read address.
Table 112.  Configuration Options for Data Generation
Toolkit GUI Tab Toolkit GUI Parameter Register Name Description
Data Seed/Fixed Pattern TG_DATA_SEED Specifies an initial value to the data generator corresponding to the index value.
PRBS and Fixed Pattern radio buttons TG_DATA_MODE Specifies whether to treat the initial value of the data generator of corresponding index as a seed for generating pseudo-random data (value of 0) or to keep the initial value static (value of 1).
Table 113.  Configuration Options for Data Mask Generation
Toolkit GUI Tab Toolkit GUI Parameter Register Name Description
Data Seed/Fixed Pattern TG_BYTEEN_SEED Specifies an initial value to the byte-enable generator corresponding to the index value.
PRBS and Fixed Pattern radio buttons TG_BYTEEN_MODE Specifies whether to treat the initial value of the byte-enable generator of corresponding index as a seed and generate pseudo-random data (value of 0) or to keep the initial value static (value of 1).

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