External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

Download PDF
ID 683841
Date 3/06/2023
Public
Document Table of Contents
Document Table of Contents x
1. Functional Description—UniPHY 2. Functional Description— Intel® MAX® 10 EMIF IP 3. Functional Description—Hard Memory Interface 4. Functional Description—HPS Memory Controller 5. Functional Description—HPC II Controller 6. Functional Description—QDR II Controller 7. Functional Description—RLDRAM II Controller 8. Functional Description—RLDRAM 3 PHY-Only IP 9. Functional Description—Example Designs 10. Introduction to UniPHY IP 11. Latency for UniPHY IP 12. Timing Diagrams for UniPHY IP 13. External Memory Interface Debug Toolkit 14. Upgrading to UniPHY-based Controllers from ALTMEMPHY-based Controllers
1. Functional Description—UniPHY x
1.1. I/O Pads 1.2. Reset and Clock Generation 1.3. Dedicated Clock Networks 1.4. Address and Command Datapath 1.5. Write Datapath 1.6. Read Datapath 1.7. Sequencer 1.8. Shadow Registers 1.9. UniPHY Interfaces 1.10. UniPHY Signals 1.11. PHY-to-Controller Interfaces 1.12. Using a Custom Controller 1.13. AFI 3.0 Specification 1.14. Register Maps 1.15. Ping Pong PHY 1.16. Efficiency Monitor and Protocol Checker 1.17. UniPHY Calibration Stages 1.18. Document Revision History
1.5. Write Datapath x
1.5.1. Leveling Circuitry
1.7. Sequencer x
1.7.1. Nios® II-Based Sequencer 1.7.2. RTL-based Sequencer
1.7.1. Nios® II-Based Sequencer x
1.7.1.1. Nios® II-based Sequencer Function 1.7.1.2. Nios® II-based Sequencer Architecture 1.7.1.3. Nios® II-based Sequencer SCC Manager 1.7.1.4. Nios® II-based Sequencer RW Manager 1.7.1.5. Nios® II-based Sequencer PHY Manager 1.7.1.6. Nios® II-based Sequencer Data Manager 1.7.1.7. Nios® II-based Sequencer Tracking Manager 1.7.1.8. Nios® II-based Sequencer Processor 1.7.1.9. Nios® II-based Sequencer Calibration and Diagnostics
1.8. Shadow Registers x
1.8.1. Shadow Registers Operation
1.9. UniPHY Interfaces x
1.9.1. The DLL and PLL Sharing Interface 1.9.2. The OCT Sharing Interface
1.9.1. The DLL and PLL Sharing Interface x
1.9.1.1. Sharing PLLs or DLLs 1.9.1.2. About PLL Simulation
1.9.2. The OCT Sharing Interface x
1.9.2.1. Modifying the Pin Assignment Script for QDR II and RLDRAM II
1.13. AFI 3.0 Specification x
1.13.1. Bus Width and AFI Ratio 1.13.2. AFI Parameters 1.13.3. AFI Signals
1.13.3. AFI Signals x
1.13.3.1. AFI Clock and Reset Signals 1.13.3.2. AFI Address and Command Signals 1.13.3.3. AFI Write Data Signals 1.13.3.4. AFI Read Data Signals 1.13.3.5. AFI Calibration Status Signals 1.13.3.6. AFI Tracking Management Signals
1.14. Register Maps x
1.14.1. UniPHY Register Map 1.14.2. Controller Register Map
1.15. Ping Pong PHY x
1.15.1. Ping Pong PHY Feature Description 1.15.2. Ping Pong PHY Architecture 1.15.3. Ping Pong PHY Operation
1.15.2. Ping Pong PHY Architecture x
1.15.2.1. Ping Pong Gasket 1.15.2.2. Ping Pong PHY Calibration
1.16. Efficiency Monitor and Protocol Checker x
1.16.1. Efficiency Monitor 1.16.2. Protocol Checker 1.16.3. Read Latency Counter 1.16.4. Using the Efficiency Monitor and Protocol Checker 1.16.5. Avalon® CSR Slave and JTAG Memory Map
1.17. UniPHY Calibration Stages x
1.17.1. Calibration Overview 1.17.2. Calibration Stages 1.17.3. Memory Initialization 1.17.4. Stage 1: Read Calibration Part One—DQS Enable Calibration and DQ/DQS Centering 1.17.5. Stage 2: Write Calibration Part One 1.17.6. Stage 3: Write Calibration Part Two—DQ/DQS Centering 1.17.7. Stage 4: Read Calibration Part Two—Read Latency Minimization 1.17.8. Calibration Signals 1.17.9. Calibration Time
1.17.4. Stage 1: Read Calibration Part One—DQS Enable Calibration and DQ/DQS Centering x
1.17.4.1. Guaranteed Write 1.17.4.2. DQS Enable Calibration 1.17.4.3. Centering DQ/DQS
2. Functional Description— Intel® MAX® 10 EMIF IP x
2.1. Intel® MAX® 10 EMIF Overview 2.2. External Memory Protocol Support 2.3. Intel® MAX® 10 Memory Controller 2.4. Intel® MAX® 10 Low Power Feature 2.5. Intel® MAX® 10 Memory PHY 2.6. Calibration 2.7. Sequencer Debug Information 2.8. Register Maps 2.9. Document Revision History
2.5. Intel® MAX® 10 Memory PHY x
2.5.1. Supported Topologies 2.5.2. Read Datapath 2.5.3. Write Datapath 2.5.4. Address and Command Datapath 2.5.5. Sequencer
2.6. Calibration x
2.6.1. Read Calibration 2.6.2. Write Calibration
3. Functional Description—Hard Memory Interface x
3.1. Multi-Port Front End (MPFE) 3.2. Multi-port Scheduling 3.3. MPFE Signal Descriptions 3.4. Hard Memory Controller 3.5. Hard PHY 3.6. Document Revision History
3.2. Multi-port Scheduling x
3.2.1. Port Scheduling 3.2.2. DRAM Burst Scheduling 3.2.3. DRAM Power Saving Modes
3.4. Hard Memory Controller x
3.4.1. Clocking 3.4.2. Reset 3.4.3. DRAM Interface 3.4.4. ECC 3.4.5. Bonding of Memory Controllers
3.5. Hard PHY x
3.5.1. Interconnections 3.5.2. Clock Domains 3.5.3. Hard Sequencer 3.5.4. MPFE Setup Guidelines 3.5.5. Soft Memory Interface to Hard Memory Interface Migration Guidelines 3.5.6. Bonding Interface Guidelines
4. Functional Description—HPS Memory Controller x
4.1. Features of the SDRAM Controller Subsystem 4.2. SDRAM Controller Subsystem Block Diagram 4.3. SDRAM Controller Memory Options 4.4. SDRAM Controller Subsystem Interfaces 4.5. Memory Controller Architecture 4.6. Functional Description of the SDRAM Controller Subsystem 4.7. SDRAM Power Management 4.8. DDR PHY 4.9. Clocks 4.10. Resets 4.11. Port Mappings 4.12. Initialization 4.13. SDRAM Controller Subsystem Programming Model 4.14. Debugging HPS SDRAM in the Preloader 4.15. SDRAM Controller Address Map and Register Definitions 4.16. Document Revision History
4.4. SDRAM Controller Subsystem Interfaces x
4.4.1. MPU Subsystem Interface 4.4.2. L3 Interconnect Interface 4.4.3. CSR Interface 4.4.4. FPGA-to-HPS SDRAM Interface
4.5. Memory Controller Architecture x
4.5.1. Multi-Port Front End 4.5.2. Single-Port Controller
4.5.2. Single-Port Controller x
4.5.2.1. Command Generator 4.5.2.2. Timer Bank Pool 4.5.2.3. Arbiter 4.5.2.4. Rank Timer 4.5.2.5. Write Data Buffer 4.5.2.6. ECC Block 4.5.2.7. AFI Interface 4.5.2.8. CSR Interface
4.6. Functional Description of the SDRAM Controller Subsystem x
4.6.1. MPFE Operation Ordering 4.6.2. MPFE Multi-Port Arbitration 4.6.3. MPFE SDRAM Burst Scheduling 4.6.4. Single-Port Controller Operation
4.6.4. Single-Port Controller Operation x
4.6.4.1. Command and Data Reordering 4.6.4.2. Bank Policy 4.6.4.3. Write Combining 4.6.4.4. Burst Length Support 4.6.4.5. ECC 4.6.4.6. Interleaving Options 4.6.4.7. AXI-Exclusive Support 4.6.4.8. Memory Protection 4.6.4.9. Example of Configuration for TrustZone
4.6.4.5. ECC x
4.6.4.5.1. Byte Writes 4.6.4.5.2. ECC Write Backs 4.6.4.5.3. User Notification of ECC Errors
4.10. Resets x
4.10.1. Taking the SDRAM Controller Subsystem Out of Reset
4.12. Initialization x
4.12.1. FPGA-to-SDRAM Protocol Details
4.12.1. FPGA-to-SDRAM Protocol Details x
4.12.1.1. Avalon-MM Bidirectional Port 4.12.1.2. Avalon-MM Write-Only Port 4.12.1.3. Avalon-MM Read Port 4.12.1.4. AXI Port
4.13. SDRAM Controller Subsystem Programming Model x
4.13.1. HPS Memory Interface Architecture 4.13.2. HPS Memory Interface Configuration 4.13.3. HPS Memory Interface Simulation 4.13.4. Generating a Preloader Image for HPS with EMIF
4.13.4. Generating a Preloader Image for HPS with EMIF x
4.13.4.1. Creating a Project in Platform Designer (Standard) 4.13.4.2. Creating a Top-Level File and Adding Constraints
4.14. Debugging HPS SDRAM in the Preloader x
4.14.1. Enabling UART or Semihosting Printout 4.14.2. Enabling Simple Memory Test 4.14.3. Enabling the Debug Report 4.14.4. Writing a Predefined Data Pattern to SDRAM in the Preloader
4.14.3. Enabling the Debug Report x
4.14.3.1. Analysis of Debug Report
5. Functional Description—HPC II Controller x
5.1. HPC II Memory Interface Architecture 5.2. HPC II Memory Controller Architecture 5.3. HPC II Controller Features 5.4. External Interfaces 5.5. Top-Level Signals Description 5.6. Sequence of Operations 5.7. Document Revision History
5.2. HPC II Memory Controller Architecture x
5.2.1. Backpressure Support 5.2.2. Command Generator 5.2.3. Timing Bank Pool 5.2.4. Arbiter 5.2.5. Rank Timer 5.2.6. Read Data Buffer and Write Data Buffer 5.2.7. ECC Block 5.2.8. AFI and CSR Interfaces
5.3. HPC II Controller Features x
5.3.1. Data Reordering 5.3.2. Pre-emptive Bank Management 5.3.3. Quasi-1T and Quasi-2T 5.3.4. User Autoprecharge Commands 5.3.5. Address and Command Decoding Logic 5.3.6. Low-Power Logic 5.3.7. ODT Generation Logic 5.3.8. Burst Merging 5.3.9. ECC
5.3.9. ECC x
5.3.9.1. Partial Writes 5.3.9.2. Partial Bursts
5.4. External Interfaces x
5.4.1. Clock and Reset Interface 5.4.2. Avalon® -ST Data Slave Interface 5.4.3. AXI Data Slave Interface 5.4.4. Controller-PHY Interface 5.4.5. Memory Side-Band Signals 5.4.6. Controller External Interfaces
5.4.3. AXI Data Slave Interface x
5.4.3.1. Enabling the AXI Interface 5.4.3.2. AXI Interface Parameters 5.4.3.3. AXI Interface Ports
5.5. Top-Level Signals Description x
5.5.1. Clock and Reset Signals 5.5.2. Local Interface Signals 5.5.3. Controller Interface Signals 5.5.4. CSR Interface Signals 5.5.5. Soft Controller Register Map 5.5.6. Hard Controller Register Map
6. Functional Description—QDR II Controller x
6.1. Block Description 6.2. Avalon® -MM and Memory Data Width 6.3. Signal Descriptions 6.4. Document Revision History
6.1. Block Description x
6.1.1. Avalon® -MM Slave Read and Write Interfaces 6.1.2. Command Issuing FSM 6.1.3. AFI
7. Functional Description—RLDRAM II Controller x
7.1. Block Description 7.2. User-Controlled Features 7.3. Avalon® -MM and Memory Data Width 7.4. Signal Descriptions 7.5. Document Revision History
7.1. Block Description x
7.1.1. Avalon® -MM Slave Interface 7.1.2. Write Data FIFO Buffer 7.1.3. Command Issuing FSM 7.1.4. Refresh Timer 7.1.5. Timer Module 7.1.6. AFI
7.2. User-Controlled Features x
7.2.1. Error Detection Parity 7.2.2. User-Controlled Refresh
8. Functional Description—RLDRAM 3 PHY-Only IP x
8.1. Block Description 8.2. Features 8.3. RLDRAM 3 AFI Protocol 8.4. Document Revision History
9. Functional Description—Example Designs x
9.1. UniPHY-Based Example Designs 9.2. Document Revision History
9.1. UniPHY-Based Example Designs x
9.1.1. Synthesis Example Design 9.1.2. Simulation Example Design 9.1.3. Traffic Generator and BIST Engine 9.1.4. Creating and Connecting the UniPHY Memory Interface and the Traffic Generator in Platform Designer
9.1.3. Traffic Generator and BIST Engine x
9.1.3.1. Read and Write Generation 9.1.3.2. Address and Burst Length Generation 9.1.3.3. Traffic Generator Signals 9.1.3.4. Traffic Generator Add-Ons 9.1.3.5. Traffic Generator Timeout Counter
9.1.4. Creating and Connecting the UniPHY Memory Interface and the Traffic Generator in Platform Designer x
9.1.4.1. Notes on Configuring UniPHY IP in Platform Designer
10. Introduction to UniPHY IP x
10.1. Release Information 10.2. Device Support Levels 10.3. Device Family and Protocol Support 10.4. UniPHY-Based External Memory Interface Features 10.5. System Requirements 10.6. Intel® FPGA IP Core Verification 10.7. Resource Utilization 10.8. Document Revision History
10.7. Resource Utilization x
10.7.1. DDR2, DDR3, and LPDDR2 Resource Utilization in Arria V Devices 10.7.2. DDR2 and DDR3 Resource Utilization in Arria II GZ Devices 10.7.3. DDR2 and DDR3 Resource Utilization in Stratix III Devices 10.7.4. DDR2 and DDR3 Resource Utilization in Stratix IV Devices 10.7.5. DDR2 and DDR3 Resource Utilization in Arria V GZ and Stratix V Devices 10.7.6. QDR II and QDR II+ Resource Utilization in Arria V Devices 10.7.7. QDR II and QDR II+ Resource Utilization in Arria II GX Devices 10.7.8. QDR II and QDR II+ Resource Utilization in Arria II GZ, Arria V GZ, Stratix III, Stratix IV, and Stratix V Devices 10.7.9. RLDRAM II Resource Utilization in Arria® V Devices 10.7.10. RLDRAM II Resource Utilization in Arria®  II GZ, Arria® V GZ, Stratix®  III, Stratix®  IV, and Stratix® V Devices
11. Latency for UniPHY IP x
11.1. DDR2 SDRAM LATENCY 11.2. DDR3 SDRAM LATENCY 11.3. LPDDR2 SDRAM LATENCY 11.4. QDR II and QDR II+ SRAM Latency 11.5. RLDRAM II Latency 11.6. RLDRAM 3 Latency 11.7. Variable Controller Latency 11.8. Document Revision History
12. Timing Diagrams for UniPHY IP x
12.1. DDR2 Timing Diagrams 12.2. DDR3 Timing Diagrams 12.3. QDR II and QDR II+ Timing Diagrams 12.4. RLDRAM II Timing Diagrams 12.5. LPDDR2 Timing Diagrams 12.6. RLDRAM 3 Timing Diagrams 12.7. Document Revision History
13. External Memory Interface Debug Toolkit x
13.1. User Interface 13.2. Setup and Use 13.3. Operational Considerations 13.4. Troubleshooting 13.5. Debug Report for Arria V and Cyclone V SoC Devices 13.6. On-Chip Debug Port for UniPHY-based EMIF IP 13.7. Example Tcl Script for Running the Legacy EMIF Debug Toolkit 13.8. Document Revision History
13.1. User Interface x
13.1.1. Communication 13.1.2. Calibration and Report Generation
13.2. Setup and Use x
13.2.1. General Workflow 13.2.2. Linking the Project to a Device 13.2.3. Establishing Communication to Connections 13.2.4. Selecting an Active Interface 13.2.5. Reports
13.5. Debug Report for Arria V and Cyclone V SoC Devices x
13.5.1. Enabling the Debug Report for Arria V and Cyclone V SoC Devices 13.5.2. Determining the Failing Calibration Stage for a Cyclone V or Arria V HPS SDRAM Controller
13.6. On-Chip Debug Port for UniPHY-based EMIF IP x
13.6.1. Access Protocol 13.6.2. Command Codes Reference 13.6.3. Header Files 13.6.4. Generating IP With the Debug Port 13.6.5. Example C Code for Accessing Debug Data
14. Upgrading to UniPHY-based Controllers from ALTMEMPHY-based Controllers x
14.1. Generating Equivalent Design 14.2. Replacing the ALTMEMPHY Datapath with UniPHY Datapath 14.3. Resolving Port Name Differences 14.4. Creating OCT Signals 14.5. Running Pin Assignments Script 14.6. Removing Obsolete Files 14.7. Simulating your Design 14.8. Document Revision History
1. Functional Description—UniPHY
2. Functional Description— Intel® MAX® 10 EMIF IP
3. Functional Description—Hard Memory Interface
4. Functional Description—HPS Memory Controller
5. Functional Description—HPC II Controller
6. Functional Description—QDR II Controller
7. Functional Description—RLDRAM II Controller
8. Functional Description—RLDRAM 3 PHY-Only IP
9. Functional Description—Example Designs
10. Introduction to UniPHY IP
11. Latency for UniPHY IP
12. Timing Diagrams for UniPHY IP
13. External Memory Interface Debug Toolkit
14. Upgrading to UniPHY-based Controllers from ALTMEMPHY-based Controllers

12.2.1. Configurable Traffic Generator 2.0 Configuration Options

The EMIF Configurable Traffic Generator 2.0 offers a range of configuration options for fast debugging of your external memory interface. You configure the traffic generator by modifying address-mapped registers through the simulation test bench file or by creating a configuration test stage.

Configuration Syntax

The test bench includes an example test procedure.

The syntax for writing to a configuraton register is as follows:

tg_send_cfg_write_<index>(<Register Name>, <Value to be written>);

The index value represents the index of the memory interface (which is usually 0, but can be 0/1 in ping-pong PHY mode).

The register name values are listed in the tables of configuration options, and can also be found in the altera_emif_avl_tg_defs.sv file, in the same directory as the test bench.

The final configuration command must be a write of any value to TG_START, which starts the traffic generator for the specified interface.

Configuration Options

Configuration options are divided into read/write, address, data, and data mask generation categories.
Table 110.  Configuration Options for Read/Write Generation
Toolkit GUI Tab Toolkit GUI Parameter Register Name Description
-- -- TG_START Tells the system to perform a write to this register to initiate traffic generation test.
Loops Loops TG_LOOP_COUNT Specifies the number of read/write loops to perform before completion of the test stage. A loop is a single iteration of writes and reads. Upon completion, the base address is either incremented (SEQ or RAND_SEQ) or replaced by a newly generated random address (RAND or RAND_SEQ).
Writes per block TG_WRITE_COUNT Specifies the number of writes to be performed in each loop of the test.
Reads per block TG_READ_COUNT Specifies the number of reads to be performed in each loop of the test. This register must have the same value as TG_WRITE_COUNT.
-- TG_WRITE_REPEAT_COUNT Specifies the number of times each write transaction is repeated.
-- TG_READ_REPEAT_COUNT Specifies the number of times each read transaction is repeated.
Reads per block TG_BURST_LENGTH Configures the length of each write/read burst to memory.
-- -- TG_CLEAR_FIRST_FAIL Clears the record of first failure occurrence. New failure information such as expected data, read data, and fail address, is written to the corresponding registers following the next failure.
-- -- TG_TEST_BYTEEN Toggles the byte-enable (data mask enable) register within the traffic generator which allows the current test to use byte-enable signals.
-- -- TG_DATA_MODE Specifies the source of data used for data signal generation during the test. Set to 0 to use pseudo-random data. Set to 1 to use user-specified values stored in the static data generators.
-- -- TG_BYTEEN_MODE Specifies the source of data used for byte-enable signal generation during the test. Set to 0 to use pseudo-random data. Set to 1 to use user-specified values stored in the static data generators.
Table 111.  Configuration Options for Address Generation
Toolkit GUI Tab Toolkit GUI Parameter Register Name Description
Address Start Address TG_SEQ_START_ADDR_WR_L Specifies the sequential start address (lower 32 bits).
Start address TG_SEQ_START_ADDR_WR_H Specifies the sequential start address (upper 32 bits)
Address mode TG_ADDR_MODE_WR Specifies how write addresses are generated by writing the value in parentheses to the register address. Values are: randomize the address for every write (0), increment sequentially from a specified address (1), increment sequentially from a random address (2), or perform one hot addressing (3).
Number of sequential address TG_RAND_SEQ_ADDRS_WR Specifies the number of times to increment sequentially on the random base address before generating a new random write address.
Return to start address TG_RETURN_TO_START_ADDR Return to start address in deterministic sequential address mode (if 1 is written to TG_ADDR_MODE_WR) after every loop of transactions.
Rank | Mask Mode TG_RANK_MASK_EN Specifies the rank masking mode by writing the value in parentheses to the register address. Values are: disable rank masking (0), maintain a static rank mask (1), cycle through rank masks incrementally (2).
Bank Address | Mask Mode TG_BANK_MASK_EN Specifies the bank masking mode by writing the value in parentheses to the register address. Values are: disable bank masking (0), maintain a static bank mask (1), cycle through bank masks incrementally (2), cycle through only three consecutive bank masks (3).
Row | Mask Mode TG_ROW_MASK_EN Specifies the mode for row masking by writing the value in parentheses to the register address. Values are: disable row masking (0), maintain a static row mask (1), cycle through row masks incrementally (2).
Bank Group | Mask Mode TG_BG_MASK_EN Specifies the mode for bank group masking by writing the value in parentheses to the register address. Values are: disable bank group masking (0), maintain a static bank group mask (1), cycle through bank group masks incrementally (2).
Rank | Mask Value TG_RANK_MASK Specifies the initial rank to be masked into the generated traffic generator address.
Bank Address | Mask Value TG_BANK_MASK Specifies the initial bank to be masked into the generated traffic generator address.
Row | Mask Value TG_ROW_MASK Specifies the initial row to be masked into the generated traffic generator address.
Bank Group | Mask Value TG_BG_MASK Specifies the initial bank group to be masked into the generated traffic generator address.
Sequential Address Increment TG_SEQ_ADDR_INCR Specifies the increment to use when sequentially incrementing the address. This value is used by both deterministic sequential addressing and random sequential addressing. (Refer to TG_ADDR_MODE_WR)
Start Address TG_SEQ_START_ADDR_RD_L Specifies the sequential start read address (lower 32 bits).
TG_SEQ_START_ADDR_RD_H Specifies the sequential start read address (upper 32 bits).
Address Mode TG_ADDR_MODE_RD Similar to TG_ADDR_MODE_WR but for reads.
Number of sequential address TG_RAND_SEQ_ADDRS_RD Specifies the number of times to increment the random sequential read address.
Table 112.  Configuration Options for Data Generation
Toolkit GUI Tab Toolkit GUI Parameter Register Name Description
Data Seed/Fixed Pattern TG_DATA_SEED Specifies an initial value to the data generator corresponding to the index value.
PRBS and Fixed Pattern radio buttons TG_DATA_MODE Specifies whether to treat the initial value of the data generator of corresponding index as a seed for generating pseudo-random data (value of 0) or to keep the initial value static (value of 1).
Table 113.  Configuration Options for Data Mask Generation
Toolkit GUI Tab Toolkit GUI Parameter Register Name Description
Data Seed/Fixed Pattern TG_BYTEEN_SEED Specifies an initial value to the byte-enable generator corresponding to the index value.
PRBS and Fixed Pattern radio buttons TG_BYTEEN_MODE Specifies whether to treat the initial value of the byte-enable generator of corresponding index as a seed and generate pseudo-random data (value of 0) or to keep the initial value static (value of 1).
Level Two Title