Visible to Intel only — GUID: mhi1439911628485
Ixiasoft
Visible to Intel only — GUID: mhi1439911628485
Ixiasoft
12.2.1.1. Test Information
The following example illustrates the syntax of a register read:
integer <Variable Name>;
tg_send_cfg_read_<index>(<Register Name>, <Variable Name>);
In hardware, you can probe the registers storing the test information (such as pnf per bit persist, first fail read address, first fail read data, and first fail expected data ).
Register Name | Description |
---|---|
TG_PASS | Returns a high value if the traffic generator passes at the end of all the test stages. |
TG_FAIL | Returns a high value if the traffic generator fails at the end of all the test stages. |
TG_FAIL_COUNT_L | Reports the failure count (lower 32 bits). |
TG_FAIL_COUNT_H | Reports the failure count(upper 32 bits). |
TG_FIRST_FAIL_ADDR_L | Reports the address of the first failure (lower 32 bits). |
TG_FIRST_FAIL_ADDR_H | Reports the address of the first failure (upper 32 bits). |
TG_FIRST_FAIL_IS_READ | First failure is Read Failure. |
TG_FIRST_FAIL_IS_WRITE | First failure is Write Failure. |
TG_VERSION | Reports the traffic generator version number. |
TG_NUM_DATA_GEN | Reports the number of data generators. |
TG_NUM_BYTEEN_GEN | Reports the number of byte-enable generators. |
TG_RANK_ADDR_WIDTH | Reports the rank address width. |
TG_BANK_ADDR_WIDTH | Reports the bank address width. |
TG_ROW_ADDR_WIDTH | Reports the row address width. |
TG_BANK_GROUP_WIDTH | Reports the bank group width. |
TG_RDATA_WIDTH | Reports the width of all data and PNF signals within the traffic generator. |
TG_DATA_PATTERN_LENGTH | Reports the length of the static pattern to be loaded into static per-pin data generators. |
TG_BYTEEN_PATTERN_LENGTH | Reports the length of the static pattern to be loaded into static per-pin byte-enable generators. |
TG_MIN_ADDR_INCR | Reports the minimum address increment permitted for sequential and random-sequential address generation. |
TG_ERROR_REPORT | Reports error bits. Refer to Error Report Register Bits for details. |
TG_PNF | Read the persistent PNF per bit as an array of 32-bit entries. |
TG_FAIL_EXPECTED_DATA | Reports the first failure expected data. This is read as an array of 32-bit entries. |
TG_FAIL_READ_DATA | Reports the first failure read data. This is read as an array of 32-bit entries. |
The configuration error report register contains information on common misconfigurations of the traffic generator. The bit corresponding to a given configuration error is set high when that configuration error is detected. Ensure that all bits in this register are low, to avoid test failures or unexpected behavior due to improper configuration.
Bit Index (LSB = 0x0) | Bit Name | Description of Error |
---|---|---|
0 | ERR_MORE_READS_THAN_WRITES | You have requested more read transactions per loop than write transactions per loop. |
1 | ERR_BURSTLENGTH_GT_SEQ_ADDR_INCR | The configured burst length is greater than the configured sequential address increment when address generation is in sequential or random sequential mode. |
2 | ERR_ADDR_DIVISIBLE_BY_GT_SEQ_ADDR_INCR | The configured sequential address increment is less than the minimum required address increment when address generation is in sequential or random sequential mode. |
3 | ERR_SEQ_ADDR_INCR_NOT_DIVISIBLE | The configured sequential address increment is not a multiple of the minimum required address increment when address generation is in sequential or random sequential mode. |
4 | ERR_READ_AND_WRITE_START_ADDRS_DIFFER | The configured start addresses for reads and writes are different when address generation is in sequential mode. |
5 | ERR_ADDR_MODES_DIFFERENT | The configured address modes for reads and writes are different. |
6 | ERR_NUMBER_OF_RAND_SEQ_ADDRS_DIFFERENT | The configured number of random sequential addresses for reads and writes are different when address generation is in random sequential mode. |
7 | ERR_REPEATS_SET_TO_ZERO | The number of read and/or write repeats is set to 0. |
8 | ERR_BOTH_BURST_AND_REPEAT_MODE_ACTIVE | The burst length is set greater than 1 and read/write requests are set greater than 1. |
9-31 | Reserved | -- |