External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
Document Table of Contents

12.2.3. Signal Splitter Component

The signal splitter (altera_emif_sig_splitter) is an internal IP component which receives a single signal as its input and passes that signal directly to n outputs, where n is an interger value equal to or greater than 1. The signal splitter is useful because Qsys does not directly allow one-to-many connections for conduit interfaces.

The signal splitter contains no logic or memory elements. When you configure the signal splitter to have exactly one output port, it is functionally identical to a single wire, and can be replaced by one with no loss of performance.

The rzq_splitter is an instantiation of the signal splitter component specifically for the RZQ signal. The signal splitter facilitates the sharing of one RZQ signal among multiple memory interfaces in an EMIF example design.