External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
Document Table of Contents

16.10. Traffic Generator 2.0

The Traffic Generator 2.0 lets you emulate traffic to the external memory, and helps you test, debug, and understand the performance of your external memory interface on hardware in a standalone fashion, without having to incorporate your entire design.

The Traffic Generator 2.0 lets you customize data patterns being written to the memory, address locations accessed in the memory, and the order of write and read transactions. You can use the traffic generator code with any FPGA architecture and memory protocol.