16.10.1. Configuring the Traffic Generator 2.0
When you generate the example design in the parameter editor, the traffic generator module and EMIF IP are generated together. If you have an example design with the Traffic Generator 2.0 enabled, you can configure the traffic pattern using the EMIF Debug Toolkit.
Generating the External Memory Interface
- Select the FPGA and Memory parameters.
- On the Diagnostics tab, configure the following parameters:
- Select Use Configurable Avalon Traffic Generator 2.0.
- Configure the desired traffic pattern, by specifying traffic patterns to be bypassed. The traffic pattern not bypassed is issued to the memory immediately after completion of calibration. You can choose to bypass any of the following traffic patterns:
- Bypass the default traffic pattern Specifies not to use the default traffic patterns from the traffic generator. The default patterns include single read/write, byte-enabled read/write, and block read/write.
- Bypass the user-configured traffic stage. Specifies to skip the stage that uses the user-defined test bench file to configure the traffic generator in simulation.
- Bypass the traffic generator repeated-writes/repeated-reads test pattern. Bypasses the traffic generator's repeat test stage, which causes every write and read to be repeated several times.
- Bypass the traffic generator stress pattern. Bypasses a test stage intended to stress-test signal integrity and memory interface calibration.
- Export Traffic Generator 2.0 configuration interface. Instantiates a port for traffic generator configuration. Use this port if the traffic generator is to be configured by user logic.
- Click Generate Example Design to generate the EMIF IP, including the Traffic Generator 2.0 design, with the traffic pattern that you have configured.
Note: If you click the Generate HDL option instead, the Traffic Generator 2.0 design is not included in the generated IP.
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