External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

16.3. Operational Considerations

Some features and considerations are of interest in particular situations.

Specifying a Particular JDI File

Correct operation of the EMIF Toolkit depends on the correct JDI being used when linking the project to the device. The JDI file is produced by the Quartus Prime Assembler, and contains a list of all system level debug nodes and their heirarchy path names. If the default .jdi file name is incorrect for your project, you must specify the correct .jdi file. The .jdi file is supplied during the link-project-to-device step, where the revision_name.jdi file in the project directory is used by default. To supply an alternative .jdi file, click on the ellipse then select the correct .jdi file.

PLL Status

When connecting to DDR-based external memory interface connections, the PLL status appears in the Establish Connection dialog box when the IP is generated to use the CSR controller port, allowing you to immediately see whether the PLL status is locked. If the PLL is not locked, no communication can occur until the PLL becomes locked and the memory interface reset is deasserted.

When you are linking your project to a device, an error message will occur if the toolkit detects that a JTAG Avalon-MM master has no clock running. You can run the Reindex Connections task to have the toolkit rescan for connections and update the status and type of found connections in the Linked Connections report.

Margining Reports

The EMIF Toolkit can display margining information showing the post-calibration data-valid windows for reads and writes. Margining information is determined by individually modifying the input and output delay chains for each data and strobe/clock pin to determine the working region. The toolkit can display margining data in both tabular and hierarchial formats.

Group Masks

To aid in debugging your external memory interface, the EMIF Toolkit allows you to mask individual groups and ranks from calibration. Masked groups and ranks are skipped during the calibration process, meaning that only unmasked groups and ranks are included in calibration. Subsequent mask operations overwrite any previous masks.

Using with Arria 10 Devices in a PHY-Only Configuration

If you want to use the Debug Toolkit with an Arria 10 EMIF IP in a PHY-only configuration, you must connect a debug clock and a reset signal to the Arria 10 external memory interface debug component. Intel recommends using the AFI clock and AFI reset for this purpose.

Note: For information about calibration stages in UniPHY-based interfaces, refer to UniPHY Calibration Stages in the Functional Description - UniPHY chapter. For information about calibration stages in Arria 10 EMIF IP, refer to Arria 10 EMIF Calibration, in the Functional Description - Arria 10 EMIF chapter.

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