Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

15.3.3. write()

Prototype:

write()

Arguments:

Verilog HDL:

bit[CDT_ADDRESS_W-1:0] address

logic[DATA_W-1:0] data

VHDL:

bit[CDT_ADDRESS_W-1:0] address

logic[DATA_W-1:0] data

bfm_id

req_if(bfm_id)

Returns:

void

Description:

Overwrites the memory content at an address you specify.
Language support: Verilog HDL, VHDL

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