Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

13.2.2. get_<role name>()

Prototype:

int <role name port width> get_<role name>()

Arguments:

Verilog HDL: None

VHDL: value

Returns:

value

Description:

Returns interface signal value from the input/bidirectional port.
Language support: Verilog HDL, VHDL

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