Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

8.4.9. get_src_ready()

Prototype:

get_src_ready()

Arguments:

Verilog HDL: None

VHDL: src_ready, bfm_id, req_if(bfm_id)

Returns:

bit

Description:

Returns the value of the source ready port.
Language support: Verilog HDL, VHDL

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