Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

16.2.1.37. signal_instructions_completed

Prototype:

signal_instructions_completed

Arguments:

Verilog HDL: None

VHDL: N.A.

Returns:

void

Description:

Signals that all instructions in the BFM has been executed.
Language support: Verilog HDL

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