Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

6.4.27. set_interface_wait_time()

Prototype:

void set_interface_wait_time(int wait_cycles, int index)

Arguments:

Verilog HDL: wait_cycles, index

VHDL: wait_cycles, index, bfm_id, req_if(bfm_id)

Returns:

void

Description:

Specifies zero or more wait states to assert in each Avalon burst cycle by driving waitrequest active. With write burst commands, each write data cycle must wait the number of cycles corresponding to the cycle index. With read burst commands, there is only one command cycle corresponding to index 0 which can be forced to wait.
Language support: Verilog HDL, VHDL

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