Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

6.4.36. set_response_timeout()

Prototype:

void set_response_timeout(int cycles)

Arguments:

Verilog HDL: None

VHDL: bfm_id, req_if(bfm_id)

Returns:

void

Description:

Sets the number of cycles that may elapse before timing out.
Language support: Verilog HDL, VHDL