Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

16.2.1.35. signal_unexpected_result_received

Prototype:

signal_unexpected_result_received

Arguments:

Verilog HDL: None

VHDL: N.A.

Returns:

void

Description:

Signals that a result has been received without an instruction.
Language support: Verilog HDL