Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Document Table of Contents get_command_burst_cycle()


int get_command_burst_cycle()


Verilog HDL: None

VHDL: command_burst_cycle, bfm_id, req_if(bfm_id)




The slave BFM receives and processes write burst commands as a discrete sequence. The number of commands corresponds to the burst count. A separate command descriptor is constructed for each write burst cycle, corresponding to a partially completed burst.

This method returns a burst cycle field specifying the burst cycle that was active when this descriptor was constructed. This facility enables the testbench to query partially completed write burst operations. The testbench can query the write data word on each burst cycle as it arrives. The testbench can begin to process it immediately. The testbench does not have to wait until the entire burst has been received. Consequently, it is possible to perform pipelined write burst processing in the testbench.

Language support: Verilog HDL, VHDL

Did you find the information on this page useful?

Characters remaining:

Feedback Message