Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents
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17.2.31. signal_result_done

Prototype:

signal_result_done

Arguments:

Verilog HDL: None

VHDL: N.A.

Returns:

void

Description:

Signals that a result has been received by the master.
Language support: Verilog HDL