Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

19.1. Avalon-MM Verilog HDL Testbench Description

At the top-level, the Verilog HDL version of the Avalon-MM testbench includes two modules:

  • The System Under Test: This module includes the Avalon-MM Master and Slaves components, the Avalon-MM Master and Slave BFMs, and the Interconnect.
  • The Test Program: The module includes Master Command, Master Response, and Slave Threads.
Figure 28. Verilog HDL Testbench for Two Avalon-MM Masters and Slaves

The Master Command Thread performs the following functions:

  • Generates random commands
  • Passes the commands to Avalon-MM Master BFM
  • Saves the commands in a FIFO for command and response verification

The Slave Thread performs the following functions:

  • Randomly sets backpressure cycles to Avalon-MM Slave BFM
  • Waits for valid commands
  • Retrieves valid commands from the Avalon-MM Slave BFM
  • Verifies commands against the expected command
  • Sends read data for read commands.
  • Saves read data in a FIFO for verification

The Master Response Thread performs the following functions:

  • Waits for valid read data responses
  • Retrieves read responses from the BFM
  • Verifies the read response against the expected data

The test program sends the following transaction types:

  • Non-bursting writes
  • Non-bursting reads
  • Bursting writes
  • Bursting reads

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