Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

10.2.8.18. signal_transaction_fifo_overflow

Prototype:

signal_transaction_fifo_overflow

Arguments:

Verilog HDL: None

VHDL: N.A.

Returns:

void

Description:

Notifies the testbench that the FIFO is full and further transactions are dropped.
Language support: Verilog HDL

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