Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

16.2.1.8. get_result_delay()

Prototype:

int get_result_delay()

Arguments:

Verilog HDL: None

VHDL: result_delay, bfm_id, req_if(bfm_id)

Returns:

Width of the data (ci_data_t)that can contain the following variables:
  • [Word_width-1:0]
  • [Ext_width-1:0]
  • [Addr_width-1:0]

Description:

Returns the result delay.
Language support: Verilog HDL, VHDL

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