Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

18.2.3. Running the Simulation

In this section, you run a simulation in the ModelSim® software on the testbench that you created. To complete this simulation, use the test program provided in the design files to provide the stimulus.
  1. Navigate to <working_directory> avst/user_test_program_<quartus_version> . <quartus_version> is classic for Quartus Prime Standard and pro for Quartus Prime Pro.
  2. Start the ModelSim software.
  3. On the Compile menu, click Compile Options.
  4. Click the Verilog & System Verilog tab.
  5. In the Language Syntax box, select Use SystemVerilog and click OK.
  6. On the File menu, click Load > Macro File.
    Note: Ensure you activate your cursor in the Transcript window, otherwise the Load function is disabled.
  7. Select load_sim.tcl, and click Open. The Tcl file creates a new working library, compiles all source files and loads signals into the ModelSim waveform viewer.
  8. To run the simulation, type the following command in the ModelSim® transcript console:
    run 1200 ns
    The Transcript window displays text messages tracking the simulation.

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