10. Avalon-ST Monitor
The Avalon-ST Monitor is implemented in SystemVerilog and uses the SystemVerilog Assertion (SVA) language. The SVA language is supported by the Synopsys VCS, and Mentor Graphics Questa. If you are using ModelSim, the monitor component still compiles and simulates, but the assertion checking is disabled.
The following figure shows a testbench that uses an Avalon-ST Monitor to test components with Avalon-ST interfaces. This figure illustrates that the monitor’s Avalon-ST source interface is connected to the DUT’s Avalon-ST sink interface. An Avalon-ST sink interface is connected to the DUT’s Avalon-ST source interface. The test program communicates with the monitor. It uses the monitor’s assertion checking and coverage groups to assure that all legal parameter values for the DUT’s Avalon-ST interfaces are verified.
Did you find the information on this page useful?