Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

7.2.20. set_enable_a_readid_sequence()

Prototype:

set_enable_a_readid_sequence()

Arguments:

Verilog HDL: Boolean

VHDL: N.A.

Returns:

void

Description:

Enables an assertion that verifies if the readid sequence follows the sequence of the transactionid.
Language support: Verilog HDL