Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Document Table of Contents

18. Avalon-ST Verilog HDL Testbench

This testbench shows how to use Avalon-ST Source and Sink BFMs to verify an Avalon-ST component using a Qsys-generated testbench.
In this example, the Avalon-ST Single-Clock FIFO buffer is the DUT. The testbench includes both the Avalon-ST Source and Sink BFMs to verify the DUT behavior.

Click this link to download the testbench Avalon Verification IP Suite Design Files.

The following software and file are required to run the test:

  • Quartus Prime software
  • ModelSim software
  • The ug_avalon_verification.zip file. This .zip file includes files for the both the Avalon-ST and Avalon-MM tutorials for Quartus Prime Standard and Quartus Prime Pro.

This testbench is available for Verilog HDL. Refer to the link below for an example VHDL testbench.