Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
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4.2. Interrupt Source and Sink API


Prototype: int clear_irq()
Arguments: Verilog HDL: interrupt_bit

VHDL: interrupt_bit, bfm_id, req_if(bfm_id)

Returns: void
Description: Asserts the interrupt signal and sets the interrupt signal to 0, regardless of the value you set for Assert IRQ high in the parameter editor.
Language Support: Verilog HDL, VHDL