Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

14.2.21. signal_grant_deasserted_while_request_remain_asserted

Prototype:

signal_grant_deasserted_while_request_remain_asserted

Arguments:

Verilog HDL: None

VHDL: N.A.

Arguments:

None.

Returns:

void

Description:

Triggers when the grant signal changes value from high to low while the request signal remains asserted.
Language support: Verilog HDL

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